AI Chips Are Becoming Packaging Systems

The August 13 signal

Applied Materials’ results make packaging demand measurable

Applied Materials reported record fiscal-third-quarter revenue of $9.12 billion on August 13, up 25% from a year earlier. The company said growth in the second half of calendar 2026 should be particularly strong in DRAM, leading-edge foundry-logic and advanced packaging, and that it is adding manufacturing capacity to support projected demand through the end of the decade.

The more revealing number came on the earnings call. Reuters reported that Applied now expects its advanced-packaging revenue to grow more than 70% in calendar 2026, up from a previous expectation of more than 50%. CFO Brice Hill also said some customer discussions now extend to 2030. Those are company expectations rather than audited forecasts of the packaging market, but they show how quickly equipment demand is moving toward the steps that connect logic and memory after individual dies have been fabricated.

This is not simply another “AI is driving chip demand” earnings story. Applied’s recent product launches identify the exact manufacturing problems customers are paying to solve: flattening surfaces for hybrid bonding, filling through-silicon vias, plating fine-pitch interconnects, controlling stress around very thin memory dies, and finding defects on thick or warped heterogeneous substrates.

The underlying change is architectural. AI performance is still improved by better transistors. But an increasing share of usable system performance comes from how many compute dies and memory stacks can be brought close together, how much data can move between them, how much power the package can deliver, and how many of those complex assemblies can be manufactured at acceptable yield.

An AI accelerator is no longer well described as one chip

The word chip encourages a mental picture inherited from earlier processors: one important silicon die placed into a relatively passive package, then mounted on a circuit board. That picture is increasingly misleading for high-end AI systems.

Modern accelerators can combine several kinds of silicon inside one package. Compute dies perform matrix operations and other arithmetic. High-bandwidth memory, or HBM, supplies very large streams of model weights and intermediate data. I/O dies or chiplets can handle communication. An interposer or redistribution structure provides dense wiring among components that cannot be connected efficiently through an ordinary circuit board.

The package is therefore doing architectural work. It determines physical distance, wiring density, memory placement, power paths, heat-removal constraints and, ultimately, how effectively separately manufactured pieces behave like one computing device.

This approach is often called heterogeneous integration: instead of insisting that every function be manufactured as one enormous monolithic die on the same process, designers combine specialized pieces. That can let a company use leading-edge manufacturing where it matters most while using other processes for memory, analog or I/O functions. It can also make systems modular enough to scale beyond the practical size of one lithography exposure.

For readers following the supply chain, this changes where bottlenecks can appear. AIUpdateWatch’s explainer on N3 and CoWoS constraints describes why leading-edge fabrication and advanced packaging are separate capacity problems. A finished compute die is not yet a finished AI accelerator if it still needs scarce HBM, an interposer and complex packaging capacity.

HBM changes the geometry of compute

Large AI models repeatedly move enormous quantities of data between memory and arithmetic units. Adding more compute is useful only if the system can keep that compute supplied with data. That is why memory bandwidth has become inseparable from accelerator design.

HBM attacks the problem by stacking DRAM dies vertically and placing the memory physically close to the processor. The stack uses through-silicon vias, or TSVs, to create vertical electrical paths through silicon rather than routing every signal around the edge of each die. Multiple HBM stacks can then sit alongside compute dies on a high-density interconnect structure.

This arrangement provides far more parallel data paths than conventional memory attached farther away on a circuit board. But the electrical advantage creates a manufacturing challenge: very thin DRAM dies have to be stacked, connected and kept mechanically stable. The copper features linking layers have to line up. The surfaces being bonded need extreme flatness. Warpage that would be tolerable in a simpler package can become a yield problem when many components and fine interconnects must align across a large area.

Applied’s June packaging launch was built around these issues. Its Producer Avila 2 system deposits stress-balanced dielectric films around TSVs to support reliable stacking of 12-layer, 16-layer and future higher-layer-count HBM designs. Its Nokota VMax 2 system performs copper electrochemical deposition for TSV fill and microbump formation. These are vendor-described product capabilities, but the process steps themselves reveal where the difficulty lies: HBM scaling is as much a precision-integration problem as a memory-cell problem.

The same logic explains why local memory specifications can be deceptive when evaluating AI hardware. The important question is not only how many gigabytes a system has, but the bandwidth, topology and distance over which data has to move. AIUpdateWatch’s local AI hardware coverage looks at the smaller end of that same memory-and-compute relationship.

Packaging has become precision semiconductor manufacturing

Older packaging could sometimes be treated as a downstream assembly step. Advanced AI packages require processes whose tolerances increasingly resemble front-end semiconductor manufacturing.

Chemical mechanical planarization (CMP) is one example. Hybrid bonding can join copper wiring and surrounding dielectric material from two surfaces with very fine pitch, reducing the distance between connected dies. But the surfaces must be extraordinarily flat. Applied says its Opta Quad platform continuously measures wafer conditions during polishing and adjusts the process to control thickness variation. The significance is not the product name; it is that microscopic surface geometry can determine whether a high-density die-to-die connection yields reliably.

Electrochemical deposition matters because TSVs, copper pillars and microbumps need uniform metal fill. If local pattern differences produce uneven plating, some connections can be too high, too low or incomplete. As pitches shrink, a small variation consumes a larger fraction of the allowable error budget.

Metrology and defect review also become harder. An advanced package may combine silicon, organic materials and glass. It can be thicker and more warped than a conventional wafer while still containing features that need nanometer-scale measurement. Applied’s Q3 release says its VeritySEM 7AP is designed for thick, heterogeneous and highly warped HBM and chiplet substrates, while SEMVision G7AP extends electron-beam defect review into packaging.

These are not glamorous specifications, but they are central to economic scaling. A design that works once in a laboratory is not a commercial architecture. It has to survive thousands of process steps and produce enough good packages per wafer or panel to justify the equipment, memory and leading-edge silicon consumed.

TSMC is scaling the package as well as the transistor

TSMC’s 2026 roadmap makes the scale of this transition easier to see.

At its April North America Technology Symposium, TSMC said it was producing 5.5-reticle-size CoWoS packages. CoWoS—Chip-on-Wafer-on-Substrate—is TSMC’s family of advanced packaging technologies used to place high-performance logic and HBM in a densely connected package.

The company’s forward roadmap is more striking. TSMC says a 14-reticle-size CoWoS is planned for production in 2028 and is intended to integrate approximately 10 large compute dies and 20 HBM stacks. It then expects versions beyond 14 reticles in 2029. These are TSMC plans, not shipping 2026 products, and the final configurations will depend on customer designs. Still, the direction is unambiguous: package area and integration density are being deliberately expanded as a way to scale AI systems.

Reticle size matters because lithography tools expose only a bounded field at once. A monolithic die cannot simply expand without limit. Advanced packaging can stitch together multiple dies and large interconnect structures to build a device whose functional footprint exceeds what one lithography exposure could produce as a single die.

TSMC is also developing 3D silicon stacking through its SoIC technology and co-packaged optics through its COUPE roadmap. Each addresses a different distance problem. 2.5D packaging brings logic and HBM together across a dense interposer. 3D stacking moves dies vertically closer. Co-packaged optics seeks to move high-bandwidth optical communication closer to the compute package instead of pushing every signal through longer electrical links.

The shared purpose is to reduce the penalty of moving information. Smaller transistors make operations cheaper and denser. Advanced integration tries to keep the surrounding data movement from consuming the gains.

Bigger packages create new yield, thermal and mechanical problems

Combining more valuable components into one package does not create free scaling. It creates a larger object in which many failure mechanisms can interact.

Yield becomes multiplicative. A package that depends on multiple compute dies, many HBM stacks and thousands of interconnects needs a strategy for known-good dies, assembly yield and repair or redundancy. One defective component can threaten the value of the other expensive parts already assembled around it.

Warpage becomes harder to control. Different materials expand differently when heated. Larger substrates and more complex stacks make mechanical deformation harder to ignore. Misalignment can damage fine-pitch connections or make subsequent processing less uniform.

Thermal density increases. Bringing compute and memory closer improves bandwidth but also concentrates heat. The package must carry power in and heat out while preserving signal integrity. Three-dimensional stacks make this especially difficult because upper and lower dies do not have equal access to cooling surfaces.

Power delivery becomes part of package design. High-current accelerators need stable voltage close to the compute elements. Resistance and inductance in the delivery path can waste energy and create transient problems. The more dies are integrated, the more the electrical design of the package starts to resemble a system architecture problem.

TSMC’s own research materials identify thermal management, power delivery and yield as core 3D-integration challenges. That is an important counterweight to roadmap graphics showing ever-larger packages. The manufacturing problem grows with the architecture.

More semiconductor value is moving into integration

Applied Materials’ >70% packaging-growth expectation matters because it suggests that this architectural shift is becoming a measurable equipment market rather than remaining a specialized engineering topic.

The company has been positioning for that market in several ways. In May it agreed to acquire ASMPT’s NEXX business, which makes deposition equipment for large-area and panel-level advanced packaging. Applied said panel formats as large as 510 by 515 millimeters or more could help manufacturers build larger AI packages and improve output compared with being confined to 300-millimeter wafer geometry. In June it announced a $500 million Singapore campus that more than doubles its advanced cleanroom capacity there. The August 13 Q3 release again pointed to added manufacturing investment through the end of the decade.

For the semiconductor industry, this changes the distribution of value. Foundries still capture value from leading-edge logic. Memory companies capture value from HBM. But packaging houses, substrate suppliers, metrology vendors, bonding-tool makers, materials companies and equipment suppliers increasingly participate in the performance race because package-level integration determines how much of the silicon’s theoretical capability can be delivered as a usable system.

It also changes capital planning. An AI data center may be discussed in terms of GPU count, power and financing, as in AIUpdateWatch’s analysis of AI compute as a project-finance asset. Upstream, however, the supply of those accelerators depends on a chain that now includes advanced packaging capacity and HBM integration. More money for data centers does not instantly create more packaged accelerators if one of those manufacturing stages is constrained.

This is why semiconductor earnings need to be read by process rather than by one blended “AI exposure” label. Growth in deposition, CMP, metrology or packaging tools can reveal architectural transitions that are not obvious from total chip-unit shipments.

This does not mean transistor scaling is finished

The packaging story is sometimes exaggerated into a claim that Moore’s Law has ended and chiplets have replaced transistor scaling. The evidence does not support that simple substitution.

TSMC, Intel, Samsung and their equipment suppliers are still spending heavily on smaller and more sophisticated transistors, backside power, new gate structures, patterning and materials engineering. Applied’s August 13 release itself expects strength in leading-edge foundry-logic alongside advanced packaging. The two forms of scaling reinforce each other.

A more accurate model is that semiconductor performance has become multi-dimensional. Designers can improve a system by making individual transistors better, by increasing memory bandwidth, by shortening die-to-die links, by placing more dies in one package, by improving power delivery, or by redesigning software around the resulting topology. The best architecture may use several of those levers together.

Advanced packaging also has its own limits. Large interposers and substrates are expensive. HBM remains costly. More interfaces create more places for defects. Thermal management gets harder. A chiplet design can reduce some monolithic-die risks while introducing integration and validation work elsewhere.

So the important change is not “packaging replaces chips.” It is that the package has become part of the chip’s performance architecture. Ignoring it now produces an incomplete picture of AI hardware.

What evidence should buyers and investors watch next?

The most useful indicators are increasingly physical and operational rather than promotional.

Packaging capacity. Track actual CoWoS and other advanced-packaging output, new tool installations and ramp timing. Announced capacity matters only when it reaches production yield.

HBM supply and stack height. More memory per accelerator raises bandwidth and capacity but increases stacking and thermal demands. The transition to 12-layer, 16-layer and future higher stacks will test both memory fabrication and assembly.

Hybrid-bonding adoption. Moving from solder microbumps toward finer-pitch direct bonding can increase interconnect density, but it raises surface-planarity, cleanliness and alignment requirements. Production yield will matter more than laboratory pitch records.

Package size and substrate technology. TSMC’s roadmap toward 14-reticle CoWoS and Applied’s push into panel-level equipment both point toward larger integration areas. Watch whether substrates, warpage control and process equipment scale economically with them.

Thermal and power architecture. If package size grows faster than cooling and power-delivery capability, the system can become constrained before all compute resources are useful. Co-packaged optics is one sign that communication power is also becoming a package-level issue.

Yield disclosure. Vendor roadmaps often emphasize maximum die counts and bandwidth. Commercial success depends on how many complete systems survive manufacturing at reasonable cost. Better public evidence on yields, repair strategies and throughput would make the economics easier to assess.

AIUpdateWatch’s AI factory explainer describes the downstream infrastructure needed to keep accelerators busy once they arrive. Advanced packaging is the upstream mirror image: the increasingly complex factory problem required to make the accelerator itself.

That is why Applied Materials’ quarter is more interesting than its share-price reaction. The numbers show commercial demand moving into manufacturing steps that used to sit outside the public conversation about AI performance. The next generation of AI compute will still be sold as GPUs, accelerators and systems. Underneath those labels, more of the scaling work is happening in the package.

Primary documentation and current reporting

Sources

Evidence note: Applied Materials’ financial results are company-reported results; the >70% calendar-2026 advanced-packaging growth expectation is Reuters reporting from the company’s earnings call. Product-performance descriptions are vendor claims and are used here mainly to identify the process steps being targeted. TSMC’s 14-reticle CoWoS configuration is a forward roadmap for 2028, not current shipping capacity. The article’s broader conclusion—that advanced packaging is becoming a core AI scaling layer—is an analytical synthesis of these primary roadmaps and current demand signals, not a claim that packaging has replaced transistor scaling.